The chip industry’s big three—Intel, Samsung and Taiwan Semiconductor Manufacturing Co. (TSMC)—are “getting serious” about a new 3D device architecture that promises to solve scaling problems that persist with today’s state-of-the-art nanosheet technology, experts told EE Times.

The three largest chipmakers for the first time gave presentations in one session at the International Electron Devices Meeting (IEDM) last month, suggesting they will commercialize complementary field effect transistor (CFET) architecture within a decade, according to Naoto Horiguchi, director of the CMOS device program at global R&D organization imec.

“All the big players–Intel, Samsung, TSMC–showed their latest achievement results,” Horiguchi said. “This is the first time the ‘big three’ presented results in one session. They are getting more and more serious.”

Before the CFET era arrives, the industry will endure three generations of nanosheet architecture and related problems with CMOS components like SRAM that have stopped scaling down. That halt in scaling will force designers of high-performance computing chips to disaggregate CMOS functions like SRAM, with workarounds that splice together older technology nodes and chiplets, according to imec, which developed the CFET concept around 2016.

 ----Form EE Times